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m pd78p324, 78p324(a) mos integrated circuit the information in this document is subject to change without notice. 16-/8-bit single-chip microcomputers 1991, 1995 data sheet the m pd78p324 is a product in which the m pd78324s internal mask rom is replaced by a one-time prom or eprom. the one-time prom product, which enables writing only once, is effective for multiple-device small production of sets or early start of mass-production. the eprom product, which enables program writing, deletion, and rewriting, is the most suitable for system evaluation. the m pd78p324(a) is more reliable than the m pd78p324. the m pd78p324(a) is a product resulting from the m pd78324(a) whose internal mask rom is replaced by a one-time prom. for details of functions, please refer to the following users manual. reading this manual is indispensable especially for designing work. m pd78322 users manual: ieu-1248 features l m pd78324 compatible ? for mass-production, this can be replaced by the m pd78324 incorporated in the mask rom. l minimum instruction run time: 250 ns (with the external clock operating at 16 mhz): m pd78p324 & 78p324(a) 320 ns (with the external clock operating at 12.5 mhz): m pd78p324(a1) & 78p324(a2) l internal prom: 32768 x 8 bits ? writing enabled only once (windowless one-time prom product) ? elimination by ultraviolet light and electrical rewriting enabled (eprom product with window): m pd78p324 only l ecc circuit incorporated ? high internal prom content reliablility possible l prom programming characteristic: m pd27c1001a compatible l qtop tm microcomputer compatible remark a qtop microcomputer is a single-chip microcomputer with one-time prom for which program writing, marking, screening, and verifying is completely supported by nec. application fields l m pd78p324: fields dealing with motor control equipment. l m pd78p324(a), 78p324(a1), and 78p324(a2): automotive and transportation equipments, etc. this document describes the m pd78p324, 78p324(a), m pd78p324(a1), and m pd78p324(a2) as well. however, unless there are particular differences, the m pd78p324 is described as a representative product. prom is the representative term used for the part common to both the one-time prom product and the eprom product. document no. ic-2857 (o. d. no. ic-8315) date published january 1995 p printed in japan
m pd78p324, 78p324(a) 2 ordering information part no. package internal rom operating temperature (t a ) m pd78p324gj-5bj 74-pin plastic qfp(20 x 20 mm) one-time prom C10 to +70 c m pd78p324lp 68-pin plastic qfj( n n 950 mil) one-time prom C10 to +70 c m pd78p324kc 68-pin ceramic wqfn eprom C10 to +70 c m pd78p324kd 74-pin ceramic wqfn eprom C10 to +70 c m pd78p324gj(a)-5bj 74-pin plastic qfp(20 x 20 mm) one-time prom C40 to +85 c m pd78p324gj(a1)-5bj 74-pin plastic qfp(20 x 20 mm) one-time prom C40 to +110 c m pd78p324gj(a2)-5bj 74-pin plastic qfp(20 x 20 mm) one-time prom C40 to +125 c m pd78p324lp(a) 68-pin plastic qfj( n n 950 mil) one-time prom C40 to +85 c m pd78p324lp(a1) 68-pin plastic qfj( n n 950 mil) one-time prom C40 to +110 c m pd78p324lp(a2) 68-pin plastic qfj( n n 950 mil) one-time prom C40 to +125 c quality grade part no. quality grade m pd78p324gj-5bj standard m pd78p324lp standard m pd78p324kc standard m pd78p324kd standard m pd78p324gj(a)-5bj special m pd78p324gj(a1)-5bj special m pd78p324gj(a2)-5bj special m pd78p324lp(a) special m pd78p324lp(a1) special m pd78p324lp(a2) special please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
m pd78p324, 78p324(a) 3 differences among m pd78p324, 78p324(a), 78p324(a1), and 78p324(a2) product name parameter quality grade operating ambient tempera- ture (t a ) operating frequency minimum instruction execution time permissible pin injection current characteristics on overvoltage application dc characteristics ac characteristics a/d converter characteristics one-time prom product eprom product m pd78p324 m pd78p324(a) m pd78p324(a1) m pd78p324(a2) standard special C10 to +70 c C40 to +85 c C40 to +110 c C40 to +125 c 8 to 16 mhz 8 to 12.5 mhz 250 ns (when operated at 16 mhz) 320 ns (when operated at 12.5 mhz) none provided differ in the analog pin input leak current, the v dd supply current, and the data retention current. differ in the bus timing. differ in the analog input voltage and the a/d converter data retention current. provided provided none
m pd78p324, 78p324(a) 4 pin configuration (top view) (1) normal operation mode (a) 74-pin plastic qfp(20 x 20 mm); 74-pin ceramic wqfn p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 nc p56/a14 p57/a15 v dd av ss p70/an0 p71/an1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 p 0/rtp0 wdto v ss nc x1 x2 reset p85/to11 p84/to10 p83/to03 p82/to02 p81/to01 p80/to00 nc p34/sck p33/si/sb1 p32/so/sb0 p31/r x d p30/t x d p42/ad2 p41/ad1 p40/ad0 astb p90/rd p91/wr p92/tas p93/tmd v ss ea p07/rtp7 p06/rtp6 p05/rtp5 p04/rtp4 p03/rtp3 p02/rtp2 p01/rtp1 nc nc p72/an2 p73/an3 p74/an4 p75/an5 p76/an6 p77/an7 av ref av dd v dd p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3 p25/intp4 p26/intp5 p27/intp6 nc pd78p324gj-5bj pd78p324kd pd78p324gj(a)-5bj pd78p324gj(a1)-5bj pd78p324gj(a2)-5bj 57 56 m m m m m caution as a measure against noise, please connect the nc pin to v ss . (it is also possible to leave this pin unconnected.) remark pin-compatible with m pd78324gj.
m pd78p324, 78p324(a) 5 (b) 68-pin plastic qfj( n n 950 mil); 68-pin ceramic wqfn 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p71/an1 p70/an0 av ss v dd p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 pd78p324lp pd78p324kc pd78p324lp(a) pd78p324lp(a1) pd78p324lp(a2) p30/t x d p31/r x d p32/so/sb0 p33/si/sb1 p34/sck p80/to00 p81/to01 p82/to02 p83/to03 p84/to10 p85/to11 reset x2 x1 v ss wdto rtp /p00 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 p01/rtp1 p02/rtp2 p03/rtp3 p04/rtp4 p05/rtp5 p06/rtp6 p07/rtp7 ea v ss p93/tmd p92/tas p91/wr p90/rd astb p40/ad0 p41/ad1 p42/ad2 p27/intp6/t1 p26/intp5 p25/intp4 p24/intp3 p23/intp2 p22/intp1 p21/intp0 p20/nmi v dd av dd av ref p77/an7 p76/an6 p75/an5 p74/an4 p73/an3 p72/an2 m m m m m 0 remark pin-compatible with m pd78324lp.
m pd78p324, 78p324(a) 6 p00-p07 : port0 p20-p27 : port2 p30-p34 : port3 p40-p47 : port4 p50-p57 : port5 p70-p77 : port7 p80-p85 : port8 p90-p93 : port9 nmi : nonmakable interrupt intp0-intp6 : interrupt from peripherals rtp0-rtp7 : realtime port ti : timer input t x d : transmit data r x d : receive data sb0/so : serial bus/serial output sb1/si : serial bus/serial input sck : serial clock to00-to03 : to10, to11 : reset : reset x1, x2 : crystal wdto : watchdog timer output ea : external access tmd : turbo mode tas : turbo access strobe wr : write strobe rd : read strobe astb : address strobe ad0-ad7 : address/data bus a8-a15 : address bus an0-an7 : analog input av ref : analog reference voltage av ss : analog v ss av dd : analog v dd v dd : power supply v ss : ground nc : non-connection y t timer output
m pd78p324, 78p324(a) 7 (2) prom programming mode (reset = h, av dd = l) (a) 74-pin plastic qfp (20 x 20 mm); 74-pin ceramic wqfn cautions 1. codes marked by brackets refer to processing by pins unused in prom programming mode. l : connect to v ss individually via a resistor. g : connect to v ss . open : do not connect anything. 2. as a measure against noise, please connect the nc pin to v ss . (it is also possible to leave this pin unconnected.) d2 d1 d0 (open) v ss v pp a7 a6 a5 a4 a3 a2 a1 nc (l) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 a0 (open) v ss nc (g) (open) reset a14 a13 a12 a11 a10 a8 nc a16 a15 pgm ce oe 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 pd78p324gj-5bj pd78p324kd pd78p324gj(a)-5bj pd78p324gj(a1)-5bj pd78p324gj(a2)-5bj 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 nc av dd v dd a9 nc (l) (g) (g) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 d3 d4 d5 d6 d7 nc v dd (g) (l) (l) m m m m m
m pd78p324, 78p324(a) 8 (b) 68-pin plastic qfj( n n 950 mil); 68-pin ceramic wqfn caution codes marked by brackets refer to processing by pins unused in prom programming mode. l : connect to v ss individually via a resistor. g : connect to v ss . open : do not connect anything. a0-a16 : address bus d0-d7 : data bus ce : chip enable oe : output enable pgm : programming mode reset : av dd : v pp : programming power supply nc : non-connection y t programming mode set a9 v dd av dd (l) (g) (g) 9876543216867666564636261 pd78p324lp pd78p324kc pd78p324lp(a) pd78p324lp(a1) pd78p324lp(a2) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a1 a2 a3 a4 a5 a6 a7 v pp v ss (open) d0 d1 d2 (l) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v dd d7 d6 d5 d4 d3 (g) (l) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 oe ce pgm a15 a16 a8 a10 a11 a12 a13 a14 reset (open) (g) v ss (open) a0 m m m m m
m pd78p324, 78p324(a) 9 internal block diagram remark *: when in prom programming mode (p20) nmi intp0-intp5 (p21-p26) (p80) to00 (p81) to01 (p82) to02 (p83) to03 (p84) to10 (p85) to11 (p27) t1/intp6 (p34) sck (p32) so/sb0 (p33) si/sb1 (p30) t x d (p31) r x d programmable interrupt controller tiner/counter unit (real time pulse unit) serial interfface (sbi) (uart) exu prom peripheral ram bcu main ram alu ecc 32k bytes 768 bytes system control & bus control & prefetch control port wdt general registers 128 bytes & data memory 128 bytes micro sequence control micro rom a/d converter (10 bits) x1 x2 reset astb rd wr tas tmd ea/v pp * a8-a15 (p50-p57) ad0-ad7 (p40-p47) a0-a16* d0-d7* pgm* ce* oe* p00-p07 (realtime port) p20-p27 p30-p34 p40-p47 p50-p57 p70-p77 p80-p85 p90-p93 wdto v dd v ss 2 2 av ref av ss av dd an0-an7 (p70-p77)
m pd78p324, 78p324(a) 10 table of contents 1. list of pin functions ........................................................................................................... 11 1.1 normal operation mode ........................................................................................................... 11 1.2 prom programming mode (reset = h, av dd = l) ................................................................. 13 1.3 pin i/o circuit and unused-pin processing ....................................................................... 14 2. difference between m pd78p324 and m pd78324 .............................................................. 16 3. prom programming .............................................................................................................. 17 3.1 operation mode ............................................................................................................................ 18 3.2 procedure for prom write ...................................................................................................... 19 3.3 procedure for prom read ........................................................................................................ 21 4. erasure characteristics ( m pd78p324kc/kd only) ..................................................... 22 5. erasure window seal ( m pd78p324kc/kd only) ........................................................... 22 6. one-time prom product screening ................................................................................ 22 7. electrical specifications .................................................................................................. 23 8. package drawings ................................................................................................................ 65 9. recommended soldering conditions ........................................................................... 69 appendix a. conversion socket package drawing and recommended substrate installation pattern .................................. 71 appendix b. tools ......................................................................................................................... 73 b.1 development tools ..................................................................................................................... 73 b.2 evaluation tools ........................................................................................................................ 77 b.3 embedded software .................................................................................................................... 77
m pd78p324, 78p324(a) 11 1. list of pin functions 1.1 normal operation mode (1) port pins pin name p00-p07 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p40-p47 p50-p57 p70-p77 p80 p81 p82 p83 p84 p85 p90 p91 p92 p93 function port 0. 8-bit i/o port. i/o specifiable per bit. (operable as a real-time output port as well.) port 2. 8-bit input-only port. port 3. 5-bit i/o port. i/o specifiable per bit. port 4. 8-bit i/o port. i/o specifiable in units of eight bits. port 5. 8-bit i/o port. i/o specifiable per bit. port 7. 8-bit input-only port. port 8. 6-bit i/o port. i/o specifiable per bit. port 9. 4-bit i/o port. i/o specifiable per bit. shared pin name rtp0-rtp7 nmi intp0 intp1 intp2 intp3 intp4 intp5 intp6/ti t x d r x d so/sb0 si/sb1 sck ad0-ad7 a8-a15 an0-an7 to00 to01 to02 to03 to10 to11 rd wr tas tmd i/o i/o input i/o i/o i/o input i/o i/o
m pd78p324, 78p324(a) 12 (2) pins other than ports (1/2) i/o output input input input input output input output i/o i/o i/o output output output output function real-time output port performing pulse outputs synchro- nously with the trigger symbols from the real-time pulse unit (rpu). external interrupt request input of edge detection. a valid edge can be selected by the external interrupt mode register. non-maskable interrupt request input of edge detection. a valid edge can be selected by the external interrupt mode register. external counter clock input to timer 1 (tm1). serial data input of the asynchronous serial interface (uart). serial data output of the asynchronous serial interface (uart). serial data input in three-wire mode of the clock synchro- nous serial interface. serial data input in three-wire mode of the clock synchro- nous serial interface. serial data output in three-wire mode of the clock synchronous serial interface. serial clock i/o of the clock synchronous serial interface. address data bus for accessing external memory. address bus for accessing external memory. read signal output to external memory. write signal output to external memory. control signal output for accessing the turbo access manager ( m pd71p301) note . output from the real-time pulse unit. shared pin name p00-p07 p21 p22 p23 p24 p25 p26 p27/ti p20 p27/intp6 p31 p30 p33/sb1 p32/sb0 p32/so p33/si p34 p40-p47 p50-p57 p90 p91 p92 p93 p80 p81 p82 p83 p84 p85 pin name rtp0-rtp7 intp0 intp1 intp2 intp3 intp4 intp5 intp6 nmi ti r x d t x d si so sb0 sb1 sck ad0-ad7 a8-a15 rd wr tas tmd to00 to01 to02 to03 to10 to11 note the turbo access manager ( m pd71p301) is a maintenance product.
m pd78p324, 78p324(a) 13 (2) pins other than ports (2/2) i/o output output input input input input input function access to external memory. timing signal output for externally latching the lower address which is output from the ad0-ad7 pin. output of the signal which indicates that the watchdog timer generated a non-maskable interrupt. normally, the ea pin is connected to v dd . by connecting the ea pin to vss, the system is placed in rom-less mode to access external memory. the level of the ea pin cannot be switched over during operation. analog input to the a/d converter reference voltage input of the a/d converter. analog power of the a/d converter. ground of the a/d converter. input of the system reset. connection of the crystal oscillator for system clock generation. when clocks are supplied externally, they are input to the x1 pin and their reverse signals are input to the x2 pin. (the x2 pin can also be left unconnected.) positive power voltage. ground. internally unconnected. please connect this to vss. (it can also be left unconnected.) shared pin name p70-p77 pin name astb wdto ea an0-an7 av ref av dd av ss reset x1 x2 v dd v ss nc 1.2 prom programming mode (reset = h, av dd = l) i/o input input i/o input input input function prom programming mode setting address bus data bus program input prom enable input read strobe to prom write power positive power voltage ground internally unconnected. please connect this to v ss . (it can also be left uncon- nected.) pin name av dd reset a0-a16 d0-d7 pgm ce oe v pp v dd v ss nc
m pd78p324, 78p324(a) 14 1.3 pin i/o circuit and unused-pin processing the i/o circuits of the pins are shown in table 1-1 and figure 1-1 some of them in a simplified form. table 1-1. i/o circuit types of pins and recommended connection methods when unused pin name p00/rtp0-p07/rtp7 p20/nmi p21/intp0-p26/intp5 p27/intp6/ti p30/t x d p31/r x d p32/so/sb0 p33/si/sb1 p34/sck p40/ad0-p47/ad7 p50/a8-p57/a15 p70/an0-p77/an7 p80/to00-p83/to03 p84/to10, p85/to11 p90/rd p91/wr p92/tas p93/tmd wdto astb ea reset av dd av ref av ss v pp nc i/o circuit type 5 2 5 8 5 9 5 5 3 4 1 2 recommended connection method when unused input status: connected to v dd or v ss via a resistor individually. output status: no connection required. connected to v ss . input status: connected to v dd or v ss via a resistor individually. output status: no connection required. connected to vss. input status: connected to v dd or vss via a resistor individually. output status: no connection required. no connection required. connected to v dd . connected to v ss . connected to v dd . connected to v ss . (it is also possible to leave this unconnected.)
m pd78p324, 78p324(a) 15 figure 1-1. i/o circuits of pins type 1 type 5 type 2 type 8 type 3 type 9 type 4 this is a schmitt-triggered input which has the hysteresis characteristic. this is the push-pull input which is capable of output high- impedance (off for both p-ch and n-ch). v dd p-ch n-ch in in p-ch n-ch out v dd p-ch n-ch out v dd output disable data in p-ch n-ch comparator v ref (threshold voltage) input enable p-ch n-ch v dd in/out output disable data p-ch n-ch v dd output disable data in/out input disable
m pd78p324, 78p324(a) 16 2. differences between m pd78p324 and m pd78324 the m pd78p324 is a product in which the m pd78324s internal mask rom is replaced by a 32kb prom. therefore, these two products share the same functions, except for differences deriving from the rom specifications (for example, write and verify, etc.). their differences are shown in table 2-1 below. table 2-1. differences between m pd78p324 and m pd78324 product name parameter internal program memory (electric write) ecc circuit prom programming pin package electrical characteristics others cautions 1. the prom product and the mask rom product differ in their noise resistance volume and noise reflection. if replacement of the prom product with the mask rom product in the process of trial to mass production is being considered, ensure to make a sufficient evaluation with the cs product (not es product) of the mask rom product. 2. the m pd78p324(a)/(a1)/(a2) are one-time prom products only. the differences between the m pd78p324(a)/(a1)/(a2) and the m pd78324(a)/(a1)/(a2) are the same as those shown in the table above, except in terms of the eprom product. m pd78p324 m pd78324 one-time prom eprom mask rom (write enabled only once) (rewrite enabled) with without with without ? 68-pin plastic qfj ? 68-pin ceramic wqfn ? 68-pin plastic qfj ? 74-pin plastic qfp ? 74-pin ceramic wqfn ? 74-pin plastic qfp differ in current consumption, etc. as they differ in their circuit size and mask layout, their noise resistance volume and noise reflection differ.
m pd78p324, 78p324(a) 17 3. prom programming the m pd78p324 incorporates an electrically writable 32768-by-8-bit program prom and an 8192-by-6-bit ecc (error correcting code) prom. ecc corrects the errors in codes written in the program prom, thus improving the reliability of the prom content. figure 3-1 shows the memory map in programming mode. figure 3-1. memory map in programming mode ecc (for ecw) ecw (4 x 8) prom for ecc note (8192 x 6) program prom (32768 x 8) a004h a003h a000h 9fffh 8000h 7fffh 0000h note on the ecc prom, the lower 6 bits are valid. when programming, set the reset pin and the av dd pin to prom programming mode. the programming characteristics of the m pd78p324 are compatible with the m pd27c1001a. however, the programming mode is compatible only with the byte program mode of the m pd27c1001a. for setting on the prom programmer, please select the byte program mode of the 27c1001a mode. when using the ecc circuit, reset the lowest bit (a000.0) of the lowest byte of the ecw (ecc control word) to enable the operation of the ecc circuit. ecw is a 4-byte register which controls the operation of the ecc circuit. ecc and ecw are generated automatically with the eccgen (ecc generator) which comes with the ra78k3 assembler package. (ecc is generated in the lower 6 bits; and the upper 2 bits are fixed to 1.)
m pd78p324, 78p324(a) 18 table 3-1. pin functions in programming mode function normal operation mode programming mode address input p00-p07, p80, p20, p81-p85, p33, p34 a0-a16 data input p40-p47 d0-d07 program pulse p32 pgm chip enable p31 ce output enable p30 oe program voltage v pp mode voltage reset, av dd 3.1 operation mode when placing the microcomputer in programming write/verify mode, set it to reset = h and av dd = l. in this mode, an operation mode in table 3-2 can be selected by further setting the ce and oe pins. when reading the content of the prom, set it to read mode. process the unused pins in accordance with the instructions in the pin configuration. table 3-2. operation mode of prom programming mode program write program verify program inhibit read output disable standby reset h av dd l remark x: l or h ce l l x x l l h oe h l l h l h x pgm l h l h h x x v pp +12.5 v +5 v v dd +6.5 v +5 v d0-d7 data input data output high impedance data output high impedance high impedance
m pd78p324, 78p324(a) 19 3.2 procedure for prom write the procedure for writing into the prom is as follows (see figure 3-3). (1) fix to reset = h; and av dd = l. other unused pins are processed as directed by the pin configuration. (2) supply +6.5 v to the v dd pin; and +12.5 v to the v pp pin. enter the low level into the ce pin. (3) enter the initial address into a0-a16. (4) enter the write data into d0-d7. (5) enter the 0.1 ms program pulse (active low) into the pgm pin. (6) verify mode. check if the write data has been written or not. enter the active low pulse into the oe pin and read the write data from d0-d7. ? when written: move to (8). ? when not able to write: repeat (4) to (6). if it is not possible to write even when the repetition has been made ten times, move to (7). (7) stop the write operation as a defective device. (8) increment the address. (9) repeat (4) to (8) until the final address. the timing of the above (2) to (7) steps is shown in figure 3-2. figure 3-2. prom write/verify timing hi-z hi-z hi-z program program verify address input data input data output a0-a16 d0-d7 v pp v dd ce (input) pgm (input) oe (input) + 12.5v v dd + 6.5v v dd
m pd78p324, 78p324(a) 20 figure 3-3. write procedure flowchart start writing supply the supply voltage supply the initial address supply the write data supply the program pulse write disabled ( less than 10 times ) verify mode address increment write disabled ( 10th times ) write complete defective device final address >final address final address write ok (10) (9) (8) (6) (5) (4) (3) (2) (1) (7)
m pd78p324, 78p324(a) 21 3.3 procedure for prom read the prom content is read to the external data bus (d0-d7) in accordance with the following procedure: (1) fix to reset = h; and av dd = l. other unused pins are processed as directed by the pin configuration. (2) supply +5 v to the v dd and v pp pins. (3) enter the address of the data read into the a0-a16 pin. (4) read mode (ce = l; oe = l) (5) data is output to the d0-d7 pin. the timing of the above (2) to (5) is shown in figure 3-4. figure 3-4. prom read timing address input data output a0-a14 ce (input) oe (input) d0-d7 hi-z hi-z
m pd78p324, 78p324(a) 22 4. erasure characteristics ( m pd78p324kc/kd only) the m pd78p324kc/kd can erase (ffh) the content of the data written in the program memory and perform rewriting. the data content is erased by radiating light with a wavelength shorter than about 400 nm on the erasure window. normally, ultraviolet light with a wavelength of 254 nm is radiated. the volume of light required for erasing the data content completely is as follows: ? ultraviolet ray intensity x erasure time: 15 ws/cm 2 or more ? erasure time: 15 to 20 mins (this is so when using an ultraviolet lamp of 12,000 m w/cm 2 . however, a longer time may be required due to performance degradation of the ultraviolet ray lamp or dirt deposited on the erasure window, etc.) for erasure, make sure to place the ultraviolet ray lamp at a location within 2.5 cm from the erasure window. if the ultraviolet ray lamp is equipped with a filter, make sure that the filter is removed for radiation. 5. erasure window seal ( m pd78p324kc/kd only) if the erasure window part of the m pd78p324kc/kd is exposed to sunlight or fluorescent light for too long, the eprom data may be erased or the internal circuits may malfunction. to prevent such an accident, please ensure that the erasure window part is covered with a protective seal except when the data is going to be erased. the eprom package with window is shipped with a protective seal that is necs guarantee of quality. 6. one-time prom product screening structurally, it is not possible for nec to test the one-time prom products ( m pd78p324gj-5bj/(a)/(a1)/ (a2) and 78p324lp/(a)/(a1)/(a2) completely before shipment. therefore, it recommended that, after writing the required data, the screening be implemented to verify the prom after storing the product in the following temperature and condition. storage temperature storage time 125 c 24 hrs nec provides at a charge services including the one-time prom writing, sealing, screening and verifying under the title of qtop microcomputer. for further details, please contact an nec salesperson.
m pd78p324, 78p324(a) 23 7. electrical specifications (1) m pd78p324 electrical specifications (1/9) absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage low-level output current high-level output current analog input voltage a/d converter reference input voltage operating ambient temperature storage temperature unit v v v v v v ma ma ma ma v v c c rating C0.5 to +7.0 C0.5 to v dd +0.5 C0.5 to +13.5 C0.5 to +0.5 C0.5 to v dd +0.5 C0.5 to v dd +0.5 4.0 90 C1.0 C20 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C10 to +70 C65 to +150 symbol v dd av dd v pp av ss v i v o i ol i oh v ian av ref t a t stg condition note 1 all output pins total of all output pins all output pins total of all output pins av dd > v dd note 2 v dd 3 av dd av dd > v dd v dd 3 av dd notes 1. except p70/an0-p77/an7. 2. p70/an0-p77/an7 pins. caution if the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. in other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. be sure to use the product without exceeding these ratings. recommended operating range oscillation frequency t a v dd 8mhz f xx 16mhz C10 to +70 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io condition f = 1 mhz; 0 v except measured pins min. tup. max. unit 10 pf 20 pf 20 pf
m pd78p324, 78p324(a) 24 (1) m pd78p324 electrical specifications (2/9) oscillator characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) oscillator ceramic oscillator or crystal oscillator external clock recommended circuit parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise time, fall time (t xr , t xf ) x1 input high-/low-level width (t wxh , t wxl ) min. max. unit 8 16 mhz 8 16 mhz 020ns 25 80 ns caution when using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. ? make the wiring as short as possible. ? avoid intersecting other signal conductors. avoid approaching lines in which very high fluctuating currents run. ? make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as v ss . avoid grounding with a grand pattern in which very high currents run. ? do not fetch signals from the oscillation circuit. x2 x1 v ss c2 c1 x2 x1 x2 x1 hcmos inverter hcmos inverter or no connection required
m pd78p324, 78p324(a) 25 (1) m pd78p324 electrical specifications (3/9) recommended oscillation circuit constants ceramic oscillator recommended constant c1 (pf) c2 (pf) 30 30 15 15 incorporated incorporated product name csa8.00mt csa12.0mt csa14.74mxz040 csa16.00mx040 cst8.00mtw cst12.0mtw cst14.74mxw0c3 cst16.00mxw0c3 frequency (mhz) 8.0 12.0 14.74 16.0 8.0 12.0 14.74 16.0 manufacturer murata mfg. co., ltd.
m pd78p324, 78p324(a) 26 (1) m pd78p324 electrical specifications (4/9) dc characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) parameter low-level input voltage high-level input voltage low-level output voltage high-level output voltage input leakage current analog pin input leakage current output leakage current v dd supply current data retention voltage data retention current min. typ. max. unit 0 0.8 v 2.2 v 0.8 v dd 0.45 v v dd C1.0 v 10 m a 10 m a 10 m a 70 95 ma 35 55 ma 2.5 v 210 m a 10 50 m a symbol v il v ih1 v ih2 v ol v oh i li i lian i lo i dd1 i dd2 v dddr i dddr condition note 1 note 2 i ol = 2.0ma i oh = C400 m a note 3 0 v v i v dd note 4 0 v v ian av ref 0 v v o v dd operation mode halt mode stop mode v dddr = 2.5 v stop mode v dddr =5.0 v 10% notes 1. pins other than pins in note 2. 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3, p25/intp4, p26/intp5, p27/ intp6/ti, p32/so/sb0, p33/si/sb1, p34/sck pins. 3. pins except p20/nmi, ea/v pp , x1, x2 4. when not sampling the analog input
m pd78p324, 78p324(a) 27 (1) m pd78p324 electrical specifications (5/9) ac characteristics (t a = C10 to +70 c, v dd = +5 v 10%, v ss = 0 v, c l = 100pf) non-serial read/write operation (when connecting general-purpose memory) parameter symbol condition min. max. unit system clock cycle time t cyk 125 250 ns address setup time (vs. astb )t sast 32 ns address hold time (vs. astb )t hsta 32 ns address ? rd delay time t dar 85 ns rd ? address float time t fra 10 ns address ? data input time t daid 222 ns rd ? data input time t drid 112 ns astb ? rd delay time t dstr 42 ns data hold time (vs. rd - )t hrid 0ns rd - ? address active time t dra 50 ns rd low-level width t wrl 147 ns astb high-level width t wsth 37 ns address ? wr delay time t daw 85 ns astb ? data output time t dstod 102 ns wr ? data output time t dwod 40 ns astb ? wr delay time t dstw 42 ns data setup time (vs. wr - )t sodw 147 ns data hold time (vs. wr - )t hwod 32 ns wr - ? astb - delay time t dwst 42 ns wr low-level width t wwl 147 ns
m pd78p324, 78p324(a) 28 (1) m pd78p324 electrical specifications (6/9) t cyk -dependent bus timing definition symbol calculation formula min./max. unit t sast 0.5tC30 min. ns t hsta 0.5tC30 min. ns t dar tC40 min. ns t daid (2.5+n) tC90 max. ns t drid (1.5+n) tC75 max. ns t dstr 0.5tC20 min. ns t dra 0.5tC12 min. ns t wrl (1.5+n) tC40 min. ns t wsth 0.5tC25 min. ns t daw tC40 min. ns t dstod 0.5t+40 max. ns t dstw 0.5tC20 min. ns t sodw 1.5tC40 min. ns t hwod 0.5tC30 min. ns t dwst 0.5tC20 min. ns t wwl (1.5+n) tC40 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. among the parameters for bus timing, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 29 (1) m pd78p324 electrical specifications (7/9) serial operation (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol condition min. max. unit sck output internal divide-by-eight 1 m s serial clock cycle time t cysk sck input external clock 1 m s sck output internal divide-by-eight 420 ns serial clock low-level width t wskl sck input external clock 420 ns sck output internal divide-by-eight 420 ns serial clock high-level width t wskh sck input external clock 420 ns si setup time (vs. sck - )t srxsk 80 ns si hold time (vs. sck - )t hskrx 80 ns sck ? so delay time t dsktx r = 1 k w , c = 100pf 210 ns t cyk -dependent serial operation symbol condition calculation formula min./max. unit sck output internal divide-by-eight 8t min. ns t cysk sck input external clock 8t min. ns sck output internal divide-by-eight 4tC80 min. ns t wskl sck input external clock 4tC80 min. ns sck output internal divide-by-eight 4tC80 min. ns t wskh sck input external clock 4tC80 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. among the parameters for serial operation, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 30 (1) m pd78p324 electrical specifications (8/9) other operations (t a = C10 to +70 c, v dd = +5 v 10 %, v dd = 0 v) parameter symbol condition min. max. unit nmi high-/low-level width t wnih , t wnil analog noises removed 4 m s intp0 high-/low-level width t wioh , t wiol 1 m s intp1 high-/low-level width t wi1h , t wi1l 1 m s intp2 high-/low-level width t wi2h , t wi2l 1 m s intp3 high-/low-level width t wi3h , t wi3l 1 m s intp4 high-/low-level width t wi4h , t wi4l 1 m s intp5 high-/low-level width t wi5h , t wi5l 1 m s intp6 high-/low-level width t wi6h , t wi6l 1 m s reset high-/low-level width t wrsh , t wrsl analog noises removed 3.5 m s ti high-/low-level width t wtih , t wtil 1 m s v dd rise/fall time t rvd , t fvd 200 m s other t cyk -dependent operations symbol calculation formula min./max. unit t wioh 8t min. ns t wiol 8t min. ns t wi1h 8t min. ns t wi1l 8t min. ns t wi2h 8t min. ns t wi2l 8t min. ns t wi3h 8t min. ns t wi3l 8t min. ns t wi4h 8t min. ns t wi4l 8t min. ns t wi5h 8t min. ns t wi5l 8t min. ns t wi6h 8t min. ns t wi6l 8t min. ns t wtih 8t min. ns t wtil 8t min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. only the parameters listed in this table depend on t cyk .
m pd78p324, 78p324(a) 31 (1) m pd78p324 electrical specifications (9/9) ac timing test point a/d converter characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C0.5 v av dd v dd ) parameter resolution total error note1 quantization error conversion time sampling time zero-scale error note1 full-scale error note 1 non-linear error note 1 analog input voltage note 2 analog input impedance reference voltage av ref current av dd supply current a/d converter data retention current min. typ. max. unit 10 bit 0.4 %fsr 0.7 %fsr 1/2 lsb 144 t cyk 24 t cyk 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 0av dd v 10 m w note 3 3.4 av dd v 1.0 3.0 ma 2.0 6.0 ma 215 m a 10 50 m a symbol t conv t samp v ian r an av ref ai ref ai dd ai dddr condition 4.5 v av ref av dd 3.5 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd when not sampled when sampled operation mode av dddr = 2.5 v stop mode av dddr =5 v 10% notes 1. quantization error excluded. 2. when C0.3 v v ian 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed at a resolution of 10 bits. when av ref v ian av dd , the conversion result is 3ffh. 3. the analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (the values in the diagram are typ. values; therefore, they are not assured.) 0.8v dd or 2.2v 0.8v 0.8v dd or 2.2v 0.8v test point v dd 0v 20k w 10pf 30pf analog input pin ( input capacitance included )
m pd78p324, 78p324(a) 32 (2) m pd78p324(a) electrical specifications (1/9) absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage low-level output current high-level output current analog input voltage a/d converter reference input voltage operating ambient temperature storage temperature unit v v v v v v ma ma ma ma v v c c rating C0.5 to +7.0 C0.5 to v dd +0.5 C0.5 to +13.5 C0.5 to +0.5 C0.5 to v dd +0.5 C0.5 to v dd +0.5 4.0 90 C1.0 C20 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C40 to +85 C65 to +150 symbol v dd av dd v pp av ss v i v o i ol i oh v ian av ref t a t stg condition notes 1, 2 all output pins total of all output pins all output pins total of all output pins av dd > v dd notes 2, 3 v dd 3 av dd av dd > v dd v dd 3 av dd notes 1. except p70/an0-p77/an7. 2. the overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. p70/an0-p77/an7 pins. caution if the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. in other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. be sure to use the product without exceeding these ratings.
m pd78p324, 78p324(a) 33 (2) m pd78p324(a) electrical specifications (2/9) permissible pin injection current characteristics in overvoltage application (t a = C40 to +85 c, v dd = +5 v 10%, v ss = 0 v) parameter positive injection current (v in > v dd ) negative injection current (v in < v ss ) symbol i ijh1 i ijh2 i ijh i ijl1 i ijl2 i ijl min. typ. max. unit 10 ma 0.5 ma 3ma 1ma 100 ma 5ma C4 ma C0.4 ma C4 ma C0.3 ma C40 ma C3 ma condition peak value mean value 1 pin peak value mean value peak value total of all input pins mean value peak value mean value 1 pin peak value mean value peak value total of all input pins mean value input ports other than ann (n = 0-7) ann (n = 0-7) input ports other than ann (n = 0-7) ann (n = 0-7) cautions 1. when the injection current has run into the analog input pin (ann: n = 0-7), the a/d conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2lsb. 2. the mean value (absolute value) of the pin injected current is as follows: mean value = ((1/t) | i(t) | 3/2 dt) 2/3 in this, i(t) refers to the pin injected current. the maximum value of |i(t)| is the peak value. recommended operating range oscillation frequency t a v dd 8mhz f xx 16mhz C40 to +85 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io condition f = 1 mhz; 0 v except measured pins min. tup. max. unit 10 pf 20 pf 20 pf t 0
m pd78p324, 78p324(a) 34 (2) m pd78p324(a) electrical specifications (3/9) oscillator characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) oscillator ceramic oscillator or crystal oscillator external clock recommended circuit parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise time, fall time (t xr , t xf ) x1 input high-/low-level width (t wxh , t wxl ) min. max. unit 8 16 mhz 8 16 mhz 020ns 25 80 ns caution when using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. ? make the wiring as short as possible. ? avoid intersecting other signal conductors. avoid approaching lines in which very high fluctuating currents run. ? make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as v ss . avoid grounding with a grand pattern in which very high currents run. ? do not fetch signals from the oscillation circuit. x2 x1 v ss c2 c1 x2 x1 x2 x1 hcmos inverter hcmos inverter or no connection required
m pd78p324, 78p324(a) 35 (2) m pd78p324(a) electrical specifications (4/9) dc characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter low-level input voltage high-level input voltage low-level output voltage high-level output voltage input leakage current analog pin input leakage current output leakage current v dd supply current data retention voltage data retention current min. typ. max. unit 0 0.8 v 2.2 v 0.8 v dd 0.45 v v dd C1.0 v 10 m a 1 m a 10 m a 70 95 ma 35 55 ma 2.5 v 210 m a 10 50 m a symbol v il v ih1 v ih2 v ol v oh i li i lian i lo i dd1 i dd2 v dddr i dddr condition note 1 note 2 i ol = 2.0ma i oh = C400 m a note 3 0 v v i v dd note 4 0 v v ian av ref 0 v v o v dd operation mode halt mode stop mode v dddr = 2.5 v stop mode v dddr =5.0 v 10% notes 1. pins other than pins in note 2. 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3, p25/intp4, p26/intp5, p27/ intp6/ti, p32/so/sb0, p33/si/sb1, p34/sck pins. 3. pins except p20/nmi, ea/v pp , x1, x2 4. when not sampling the analog input
m pd78p324, 78p324(a) 36 (2) m pd78p324(a) electrical specifications (5/9) ac characteristics (t a = C40 to +85 c, v dd = +5 v 10%, v ss = 0 v, c l = 100pf) non-serial read/write operation (when connecting general-purpose memory) parameter symbol condition min. max. unit system clock cycle time t cyk 125 250 ns address setup time (vs. astb )t sast 32 ns address hold time (vs. astb )t hsta 32 ns address ? rd delay time t dar 85 ns rd ? address float time t fra 10 ns address ? data input time t daid 222 ns rd ? data input time t drid 112 ns astb ? rd delay time t dstr 42 ns data hold time (vs. rd - )t hrid 0ns rd - ? address active time t dra 50 ns rd low-level width t wrl 147 ns astb high-level width t wsth 37 ns address ? wr delay time t daw 85 ns astb ? data output time t dstod 102 ns wr ? data output time t dwod 40 ns astb ? wr delay time t dstw 42 ns data setup time (vs. wr - )t sodw 147 ns data hold time (vs. wr - )t hwod 32 ns wr - ? astb - delay time t dwst 42 ns wr low-level width t wwl 147 ns
m pd78p324, 78p324(a) 37 (2) m pd78p324(a) electrical specifications (6/9) t cyk -dependent bus timing definition symbol calculation formula min./max. unit t sast 0.5tC30 min. ns t hsta 0.5tC30 min. ns t dar tC40 min. ns t daid (2.5+n) tC90 max. ns t drid (1.5+n) tC75 max. ns t dstr 0.5tC20 min. ns t dra 0.5tC12 min. ns t wrl (1.5+n) tC40 min. ns t wsth 0.5tC25 min. ns t daw tC40 min. ns t dstod 0.5t+40 max. ns t dstw 0.5tC20 min. ns t sodw 1.5tC40 min. ns t hwod 0.5tC30 min. ns t dwst 0.5tC20 min. ns t wwl (1.5+n) tC40 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. among the parameters for bus timing, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 38 (2) m pd78p324(a) electrical specifications (7/9) serial operation (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol condition min. max. unit sck output internal divide-by-eight 1 m s serial clock cycle time t cysk sck input external clock 1 m s sck output internal divide-by-eight 420 ns serial clock low-level width t wskl sck input external clock 420 ns sck output internal divide-by-eight 420 ns serial clock high-level width t wskh sck input external clock 420 ns si setup time (vs. sck - )t srxsk 80 ns si hold time (vs. sck - )t hskrx 80 ns sck ? so delay time t dsktx r = 1 k w , c = 100pf 210 ns t cyk -dependent serial operation symbol condition calculation formula min./max. unit sck output internal divide-by-eight 8t min. ns t cysk sck input external clock 8t min. ns sck output internal divide-by-eight 4tC80 min. ns t wskl sck input external clock 4tC80 min. ns sck output internal divide-by-eight 4tC80 min. ns t wskh sck input external clock 4tC80 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. among the parameters for serial operation, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 39 (2) m pd78p324(a) electrical specifications (8/9) other operations (t a = C40 to +85 c, v dd = +5 v 10 %, v dd = 0 v) parameter symbol condition min. max. unit nmi high-/low-level width t wnih , t wnil analog noises removed 4 m s intp0 high-/low-level width t wioh , t wiol 1 m s intp1 high-/low-level width t wi1h , t wi1l 1 m s intp2 high-/low-level width t wi2h , t wi2l 1 m s intp3 high-/low-level width t wi3h , t wi3l 1 m s intp4 high-/low-level width t wi4h , t wi4l 1 m s intp5 high-/low-level width t wi5h , t wi5l 1 m s intp6 high-/low-level width t wi6h , t wi6l 1 m s reset high-/low-level width t wrsh , t wrsl analog noises removed 3.5 m s ti high-/low-level width t wtih , t wtil 1 m s v dd rise/fall time t rvd , t fvd 200 m s other t cyk -dependent operations symbol calculation formula min./max. unit t wioh 8t min. ns t wiol 8t min. ns t wi1h 8t min. ns t wi1l 8t min. ns t wi2h 8t min. ns t wi2l 8t min. ns t wi3h 8t min. ns t wi3l 8t min. ns t wi4h 8t min. ns t wi4l 8t min. ns t wi5h 8t min. ns t wi5l 8t min. ns t wi6h 8t min. ns t wi6l 8t min. ns t wtih 8t min. ns t wtil 8t min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. only the parameters listed in this table depend on t cyk .
m pd78p324, 78p324(a) 40 (2) m pd78p324(a) electrical specifications (9/9) ac timing test point a/d converter characteristics (t a = C40 to +85 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C0.5 v av dd v dd ) parameter resolution total error note 1 quantization error conversion time sampling time zero-scale error note 1 full-scale error note 1 non-linear error note 1 analog input voltage note 2 analog input impedance reference voltage av ref current av dd supply current a/d converter data retention current min. typ. max. unit 10 bit 0.4 %fsr 0.7 %fsr 1/2 lsb 144 t cyk 24 t cyk 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 0av dd v 10 m w note 3 3.4 av dd v 1.0 3.0 ma 2.0 6.0 ma 215 m a 10 50 m a symbol t conv t samp v ian r an av ref ai ref ai dd ai dddr condition 4.5 v av ref av dd 3.5 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd when not sampled when sampled operation mode av dddr = 2.5 v stop mode av dddr =5 v 10% notes 1. quantization error excluded. 2. when v ian = 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed at a resolution of 10 bits. when av ref v ian av dd , the conversion result is 3ffh. 3. the analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (the values in the diagram are typ. values; therefore, they are not assured.) 20k w 10pf 30pf analog input pin ( input capacitance included ) 0.8v dd or 2.2v 0.8v 0.8v dd or 2.2v 0.8v test point v dd 0v
m pd78p324, 78p324(a) 41 (3) m pd78p324(a1) electrical specifications (1/9) absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage low-level output current high-level output current analog input voltage a/d converter reference input voltage operating ambient temperature storage temperature unit v v v v v v ma ma ma ma v v c c rating C0.5 to +7.0 C0.5 to v dd +0.5 C0.5 to +13.5 C0.5 to +0.5 C0.5 to v dd +0.5 C0.5 to v dd +0.5 4.0 90 C1.0 C20 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C40 to +110 C65 to +150 symbol v dd av dd v pp av ss v i v o i ol i oh v ian av ref t a t stg condition notes 1, 2 all output pins total of all output pins all output pins total of all output pins av dd > v dd notes 2, 3 v dd 3 av dd av dd > v dd v dd 3 av dd notes 1. except p70/an0-p77/an7. 2. the overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. p70/an0-p77/an7 pins. caution if the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. in other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. be sure to use the product without exceeding these ratings.
m pd78p324, 78p324(a) 42 (3) m pd78p324(a1) electrical specifications (2/9) permissible pin injection current characteristics in overvoltage application (t a = C40 to +110 c, v dd = +5 v 10%, v ss = 0 v) parameter positive injection current (v in > v dd ) negative injection current (v in < v ss ) symbol i ijh1 i ijh2 i ijh i ijl1 i ijl2 i ijl min. typ. max. unit 10 ma 0.5 ma 3ma 1ma 100 ma 5ma C4 ma C0.4 ma C4 ma C0.3 ma C40 ma C3 ma condition peak value mean value 1 pin peak value mean value peak value total of all input pins mean value peak value mean value 1 pin peak value mean value peak value total of all input pins mean value input ports other than ann (n = 0-7) ann (n = 0-7) input ports other than ann (n = 0-7) ann (n = 0-7) cautions 1. when the injection current has run into the analog input pin (ann: n = 0-7), the a/d conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2lsb. 2. the mean value (absolute value) of the pin injected current is as follows: mean value = ((1/t) | i(t) | 3/2 dt) 2/3 in this, i(t) refers to the pin injected current. the maximum value of |i(t)| is the peak value. recommended operating range oscillation frequency t a v dd 8mhz f xx 12.5 mhz C40 to +110 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter input capacitance output capacitance i/o cpapacitance symbol c i c o c io condition f = 1 mhz; 0 v except measured pins min. tup. max. unit 10 pf 20 pf 20 pf t 0
m pd78p324, 78p324(a) 43 (3) m pd78p324(a1) electrical specifications (3/9) oscillator characteristics (t a = C40 to +110 c, v dd = +5 v 10 %, v ss = 0 v) oscillator ceramic oscillator or crystal oscillator external clock recommended circuit parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise time, fall time (t xr , t xf ) x1 input high-/low-level width (t wxh , t wxl ) min. max. unit 8 12.5 mhz 8 12.5 mhz 020ns 46 100 ns caution when using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. ? make the wiring as short as possible. ? avoid intersecting other signal conductors. avoid approaching lines in which very high fluctuating currents run. ? make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as v ss . avoid grounding with a grand pattern in which very high currents run. ? do not fetch signals from the oscillation circuit. x2 x1 v ss c2 c1 x2 x1 x2 x1 hcmos inverter hcmos inverter or no connection required
m pd78p324, 78p324(a) 44 (3) m pd78p324(a1) electrical specifications (4/9) dc characteristics (t a = C40 to +110 c, v dd = +5 v 10 %, v ss = 0 v) parameter low-level input voltage high-level input voltage low-level output voltage high-level output voltage input leakage current analog pin input leakage current output leakage current v dd supply current data retention voltage data retention current min. typ. max. unit 0 0.8 v 2.2 v 0.8 v dd 0.45 v v dd C1.0 v 10 m a 2 m a 10 m a 65 87 ma 25 48 ma 2.5 v 2 100 m a 10 1000 m a symbol v il v ih1 v ih2 v ol v oh i li i lian i lo i dd1 i dd2 v dddr i dddr condition note 1 note 2 i ol = 2.0ma i oh = C400 m a note 3 0 v v i v dd note 4 0 v v ian av ref 0 v v o v dd operation mode halt mode stop mode v dddr = 2.5 v stop mode v dddr =5.0 v 10% notes 1. pins other than pins in note 2. 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3, p25/intp4, p26/intp5, p27/ intp6/ti, p32/so/sb0, p33/si/sb1, p34/sck pins. 3. pins except p20/nmi, ea/v pp , x1, x2 4. when not sampling the analog input
m pd78p324, 78p324(a) 45 (3) m pd78p324(a1) electrical specifications (5/9) ac characteristics (t a = C40 to +110 c, v dd = +5 v 10%, v ss = 0 v, c l = 100pf) non-serial read/write operation (when connecting general-purpose memory) parameter symbol condition min. max. unit system clock cycle time t cyk 160 250 ns address setup time (vs. astb )t sast 40 ns address hold time (vs. astb )t hsta 50 ns address ? rd delay time t dar 120 ns rd ? address float time t fra 10 ns address ? data input time t daid 310 ns rd ? data input time t drid 165 ns astb ? rd delay time t dstr 60 ns data hold time (vs. rd - )t hrid 0ns rd - ? address active time t dra 68 ns rd low-level width t wrl 191 ns astb high-level width t wsth 55 ns address ? wr delay time t daw 120 ns astb ? data output time t dstod 120 ns wr ? data output time t dwod 40 ns astb ? wr delay time t dstw 60 ns data setup time (vs. wr - )t sodw 191 ns data hold time (vs. wr - )t hwod 50 ns wr - ? astb - delay time t dwst 60 ns wr low-level width t wwl 195 ns
m pd78p324, 78p324(a) 46 (3) m pd78p324(a1) electrical specifications (6/9) t cyk -dependent bus timing definition symbol calculation formula min./max. unit t sast 0.5tC40 min. ns t hsta 0.5tC30 min. ns t dar tC40 min. ns t daid (2.5+n) tC90 max. ns t drid (1.5+n) tC75 max. ns t dstr 0.5tC20 min. ns t dra 0.5tC12 min. ns t wrl (1.5+n) tC49 min. ns t wsth 0.5tC25 min. ns t daw tC40 min. ns t dstod 0.5t+40 max. ns t dstw 0.5tC20 min. ns t sodw 1.5tC49 min. ns t hwod 0.5tC30 min. ns t dwst 0.5tC20 min. ns t wwl (1.5+n) tC45 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. among the parameters for bus timing, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 47 (3) m pd78p324(a1) electrical specifications (7/9) serial operation (t a = C40 to +110 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol condition min. max. unit sck output internal divide-by-eight 1280 m s serial clock cycle time t cysk sck input external clock 1280 m s sck output internal divide-by-eight 560 ns serial clock low-level width t wskl sck input external clock 560 ns sck output internal divide-by-eight 560 ns serial clock high-level width t wskh sck input external clock 560 ns si setup time (vs. sck - )t srxsk 80 ns si hold time (vs. sck - )t hskrx 80 ns sck ? so delay time t dsktx r = 1 k w , c = 100pf 210 ns t cyk -dependent serial operation symbol condition calculation formula min./max. unit sck output internal divide-by-eight 8t min. ns t cysk sck input external clock 8t min. ns sck output internal divide-by-eight 4tC80 min. ns t wskl sck input external clock 4tC80 min. ns sck output internal divide-by-eight 4tC80 min. ns t wskh sck input external clock 4tC80 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. among the parameters for serial operation, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 48 (3) m pd78p324(a1) electrical specifications (8/9) other operations (t a = C40 to +110 c, v dd = +5 v 10 %, v dd = 0 v) parameter symbol condition min. max. unit nmi high-/low-level width t wnih , t wnil analog noises removed 4 m s intp0 high-/low-level width t wioh , t wiol 1280 ns intp1 high-/low-level width t wi1h , t wi1l 1280 ns intp2 high-/low-level width t wi2h , t wi2l 1280 ns intp3 high-/low-level width t wi3h , t wi3l 1280 ns intp4 high-/low-level width t wi4h , t wi4l 1280 ns intp5 high-/low-level width t wi5h , t wi5l 1280 ns intp6 high-/low-level width t wi6h , t wi6l 1280 ns reset high-/low-level width t wrsh , t wrsl analog noises removed 3.5 m s ti high-/low-level width t wtih , t wtil 1280 ns v dd rise/fall time t rvd , t fvd 200 m s other t cyk -dependent operations symbol calculation formula min./max. unit t wioh 8t min. ns t wiol 8t min. ns t wi1h 8t min. ns t wi1l 8t min. ns t wi2h 8t min. ns t wi2l 8t min. ns t wi3h 8t min. ns t wi3l 8t min. ns t wi4h 8t min. ns t wi4l 8t min. ns t wi5h 8t min. ns t wi5l 8t min. ns t wi6h 8t min. ns t wi6l 8t min. ns t wtih 8t min. ns t wtil 8t min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. only the parameters listed in this table depend on t cyk .
m pd78p324, 78p324(a) 49 (3) m pd78p324(a1) electrical specifications (9/9) ac timing test point a/d converter characteristics (t a = C40 to +110 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C0.5 v av dd v dd ) parameter resolution total error note 1 quantization error conversion time sampling time zero-scale error note 1 full-scale error note 1 non-linear error note 1 analog input voltage note 2 analog input impedance reference voltage av ref current av dd supply current a/d converter data retention current min. typ. max. unit 10 bit 0.4 %fsr 0.7 %fsr 1/2 lsb 144 t cyk 24 t cyk 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 0av dd v 10 m w note 3 3.4 av dd v 1.0 3.0 ma 2.0 6.0 ma 2 100 m a 10 1000 m a symbol t conv t samp v ian r an av ref ai ref ai dd ai dddr condition 4.5 v av ref av dd 3.5 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd when not sampled when sampled operation mode av dddr = 2.5 v stop mode av dddr =5 v 10% notes 1. quantization error excluded. 2. when v ian = 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed at a resolution of 10 bits. when av ref v ian av dd , the conversion result is 3ffh. 3. the analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (the values in the diagram are typ. values; therefore, they are not assured.) 0.8v dd or 2.2v 0.8v 0.8v dd or 2.2v 0.8v test point v dd 0v 20k w 10pf 30pf analog input pin ( input capacitance included )
m pd78p324, 78p324(a) 50 (4) m pd78p324(a2) electrical specifications (1/9) absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage low-level output current high-level output current analog input voltage a/d converter reference input voltage operating ambient temperature storage temperature unit v v v v v v ma ma ma ma v v c c rating C0.5 to +7.0 C0.5 to v dd +0.5 C0.5 to +13.5 C0.5 to +0.5 C0.5 to v dd +0.5 C0.5 to v dd +0.5 4.0 90 C1.0 C20 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C0.5 to v dd +0.5 C0.5 to av dd +0.5 C40 to +125 C65 to +150 symbol v dd av dd v pp av ss v i v o i ol i oh v ian av ref t a t stg condition notes 1, 2 all output pins total of all output pins all output pins total of all output pins av dd > v dd notes 2, 3 v dd 3 av dd av dd > v dd v dd 3 av dd notes 1. except p70/an0-p77/an7. 2. the overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. p70/an0-p77/an7 pins. caution if the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. in other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. be sure to use the product without exceeding these ratings.
m pd78p324, 78p324(a) 51 (4) m pd78p324(a2) electrical specifications (2/9) permissible pin injection current characteristics in overvoltage application (t a = C40 to +125 c, v dd = +5 v 10%, v ss = 0 v) parameter positive injection current (v in > v dd ) negative injection current (v in < v ss ) symbol i ijh1 i ijh2 i ijh i ijl1 i ijl2 i ijl min. typ. max. unit 10 ma 0.5 ma 3ma 1ma 100 ma 5ma C4 ma C0.4 ma C4 ma C0.3 ma C40 ma C3 ma condition peak value mean value 1 pin peak value mean value peak value total of all input pins mean value peak value mean value 1 pin peak value mean value peak value total of all input pins mean value input ports other than ann (n = 0-7) ann (n = 0-7) input ports other than ann (n = 0-7) ann (n = 0-7) cautions. 1. when the injection current has run into the analog input pin (ann: n = 0-7), the a/d conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2lsb. 2. the mean value (absolute value) of the pin injected current is as follows: mean value = ((1/t) | i(t) | 3/2 dt) 2/3 in this, i(t) refers to the pin injected current. the maximum value of |i(t)| is the peak value. recommended operating range oscillation frequency t a v dd 8mhz f xx 12.5 mhz C40 to +125 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io condition f = 1 mhz; 0 v except measured pins min. tup. max. unit 10 pf 20 pf 20 pf t 0
m pd78p324, 78p324(a) 52 (4) m pd78p324(a2) electrical specifications (3/9) oscillator characteristics (t a = 40 to +125 c, v dd = +5 v 10 %, v ss = 0 v) oscillator ceramic oscillator or crystal oscillator external clock recommended circuit parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise time, fall time (t xr , t xf ) x1 input high-/low-level width (t wxh , t wxl ) min. max. unit 8 12.5 mhz 8 12.5 mhz 020ns 46 100 ns caution when using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. ? make the wiring as short as possible. ? avoid intersecting other signal conductors. avoid approaching lines in which very high fluctuating currents run. ? make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as v ss . avoid grounding with a grand pattern in which very high currents run. ? do not fetch signals from the oscillation circuit. x2 x1 v ss c2 c1 x2 x1 x2 x1 hcmos inverter hcmos inverter or no connection required
m pd78p324, 78p324(a) 53 (4) m pd78p324(a2) electrical specifications (4/9) dc characteristics (t a = C40 to +125 c, v dd = +5 v 10 %, v ss = 0 v) parameter low-level input voltage high-level input voltage low-level output voltage high-level output voltage input leakage current analog pin input leakage current output leakage current v dd supply current data retention voltage data retention current min. typ. max. unit 0 0.8 v 2.2 v 0.8 v dd 0.45 v v dd C1.0 v 10 m a 2 m a 10 m a 65 87 ma 25 48 ma 2.5 v 2 100 m a 10 1000 m a symbol v il v ih1 v ih2 v ol v oh i li i lian i lo i dd1 i dd2 v dddr i dddr condition note 1 note 2 i ol = 2.0ma i oh = C400 m a note 3 0 v v i v dd note 4 0 v v ian av ref 0 v v o v dd operation mode halt mode stop mode v dddr = 2.5 v stop mode v dddr =5.0 v 10% notes 1. pins other than pins in note 2. 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2, p24/intp3, p25/intp4, p26/intp5, p27/ intp6/ti, p32/so/sb0, p33/si/sb1, p34/sck pins. 3. pins except p20/nmi, ea/v pp , x1, x2 4. when not sampling the analog input
m pd78p324, 78p324(a) 54 (4) m pd78p324(a2) electrical specifications (5/9) ac characteristics (t a = C40 to +125 c, v dd = +5 v 10%, v ss = 0 v, c l = 100pf) non-serial read/write operation (when connecting general-purpose memory) parameter symbol condition min. max. unit system clock cycle time t cyk 160 250 ns address setup time (vs. astb )t sast 40 ns address hold time (vs. astb )t hsta 50 ns address ? rd delay time t dar 120 ns rd ? address float time t fra 10 ns address ? data input time t daid 310 ns rd ? data input time t drid 165 ns astb ? rd delay time t dstr 60 ns data hold time (vs. rd - )t hrid 0ns rd - ? address active time t dra 68 ns rd low-level width t wrl 191 ns astb high-level width t wsth 55 ns address ? wr delay time t daw 120 ns astb ? data output time t dstod 120 ns wr ? data output time t dwod 40 ns astb ? wr delay time t dstw 60 ns data setup time (vs. wr - )t sodw 191 ns data hold time (vs. wr - )t hwod 50 ns wr - ? astb - delay time t dwst 60 ns wr low-level width t wwl 195 ns
m pd78p324, 78p324(a) 55 (4) m pd78p324(a2) electrical specifications (6/9) t cyk -dependent bus timing definition symbol calculation formula min./max. unit t sast 0.5tC40 min. ns t hsta 0.5tC30 min. ns t dar tC40 min. ns t daid (2.5+n) tC90 max. ns t drid (1.5+n) tC75 max. ns t dstr 0.5tC20 min. ns t dra 0.5tC12 min. ns t wrl (1.5+n) tC49 min. ns t wsth 0.5tC25 min. ns t daw tC40 min. ns t dstod 0.5t+40 max. ns t dstw 0.5tC20 min. ns t sodw 1.5tC49 min. ns t hwod 0.5tC30 min. ns t dwst 0.5tC20 min. ns t wwl (1.5+n) tC45 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. among the parameters for bus timing, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 56 (4) m pd78p324(a2) electrical specifications (7/9) serial operation (t a = 40 to +125 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol condition min. max. unit sck output internal divide-by-eight 1280 m s serial clock cycle time t cysk sck input external clock 1280 m s sck output internal divide-by-eight 560 ns serial clock low-level width t wskl sck input external clock 560 ns sck output internal divide-by-eight 560 ns serial clock high-level width t wskh sck input external clock 560 ns si setup time (vs. sck - )t srxsk 80 ns si hold time (vs. sck - )t hskrx 80 ns sck ? so delay time t dsktx r = 1 k w , c = 100pf 210 ns t cyk -dependent serial operation symbol condition calculation formula min./max. unit sck output internal divide-by-eight 8t min. ns t cysk sck input external clock 8t min. ns sck output internal divide-by-eight 4tC80 min. ns t wskl sck input external clock 4tC80 min. ns sck output internal divide-by-eight 4tC80 min. ns t wskh sck input external clock 4tC80 min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. among the parameters for serial operation, only those listed in this table are dependent on t cyk .
m pd78p324, 78p324(a) 57 (4) m pd78p324(a2) electrical specifications (8/9) other operations (t a = C40 to +125 c, v dd = +5 v 10 %, v dd = 0 v) parameter symbol condition min. max. unit nmi high-/low-level width t wnih , t wnil analog noises removed 4 m s intp0 high-/low-level width t wioh , t wiol 1280 ns intp1 high-/low-level width t wi1h , t wi1l 1280 ns intp2 high-/low-level width t wi2h , t wi2l 1280 ns intp3 high-/low-level width t wi3h , t wi3l 1280 ns intp4 high-/low-level width t wi4h , t wi4l 1280 ns intp5 high-/low-level width t wi5h , t wi5l 1280 ns intp6 high-/low-level width t wi6h , t wi6l 1280 ns reset high-/low-level width t wrsh , t wrsl analog noises removed 3.5 m s ti high-/low-level width t wtih , t wtil 1280 ns v dd rise/fall time t rvd , t fvd 200 m s other t cyk -dependent operations symbol calculation formula min./max. unit t wioh 8t min. ns t wiol 8t min. ns t wi1h 8t min. ns t wi1l 8t min. ns t wi2h 8t min. ns t wi2l 8t min. ns t wi3h 8t min. ns t wi3l 8t min. ns t wi4h 8t min. ns t wi4l 8t min. ns t wi5h 8t min. ns t wi5l 8t min. ns t wi6h 8t min. ns t wi6l 8t min. ns t wtih 8t min. ns t wtil 8t min. ns remarks 1. t = t cyk = 1/f clk (f clk refers to the internal system clock frequency) 2. only the parameters listed in this table depend on t cyk .
m pd78p324, 78p324(a) 58 (4) m pd78p324(a2) electrical specifications (9/9) ac timing test point a/d converter characteristics (t a = C40 to +125 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C0.5 v av dd v dd ) parameter resolution total error note 1 quantization error conversion time sampling time zero-scale error note 1 full-scale error note 1 non-linear error note 1 analog input voltage note 2 analog input impedance reference voltage av ref current av dd supply current a/d converter data retention current min. typ. max. unit 10 bit 0.4 %fsr 0.7 %fsr 1/2 lsb 144 t cyk 24 t cyk 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 1.5 2.5 lsb 1.5 4.5 lsb 0av dd v 10 m w note 3 3.4 av dd v 1.0 3.0 ma 2.0 6.0 ma 2 100 m a 10 1000 m a symbol t conv t samp v ian r an av ref ai ref ai dd ai dddr condition 4.5 v av ref av dd 3.5 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd 4.5 v av ref av dd 3.4 v av ref av dd when not sampled when sampled operation mode av dddr = 2.5 v stop mode av dddr =5 v 10% notes 1. quantization error excluded. 2. when v ian = 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed at a resolution of 10 bits. when av ref v ian av dd , the conversion result is 3ffh. 3. the analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (the values in the diagram are typ. values; therefore, they are not assured.) 0.8v dd or 2.2v 0.8v 0.8v dd or 2.2v 0.8v test point v dd 0v 20k w 10pf 30pf analog input pin ( input capacitance included )
m pd78p324, 78p324(a) 59 non-serial read operation non-serial write operation (clk) p50-p57 (output) hi-z hi-z hi-z hi-z p40-p47 (input/output) astb (output) data (input) lower address(output) lower address(output) upper address rd (output) (clk) p50-p57 (output) p40-p47 (input/output) astb (output) wr (output) upper address upper address upper address undfined lower address(output) data (output) lower address(output) t wsth t daid t sast t hsta t hrid t fra t dstr t dar t cyk t dra t drid t wrl t sast t wsth t hsta t dstod t dstw t daw t dwod t sodw t hwod t dwst t wwl
m pd78p324, 78p324(a) 60 serial operation interrupt input timing remark n = 0-6 nmi 1ntpn sck so si t wnih t wnil t winh t winl 0.8v dd 0.8v t hskrx t srxsk t dsktx t wskl t wskh t cysk
m pd78p324, 78p324(a) 61 reset input timing ti pin input timing data retention timing t wrsh t wrsl t wtih t wtil 0.8v dd 0.8v reset ti v dd 90% v dddr 10% t fvd t rvd
m pd78p324, 78p324(a) 62 parameter high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage input current output leakage current v ddp supply voltage v pp supply voltage v ddp supply current v pp supply current symbol note 1 v ih v il i li v oh v ol v cc v pp i dd i pp condition 0 v i v ddp note 2 i oh = C400 m a i ol = 2.0 m a a9(p20/nmi) pin, 0 v o v ddp 0 v o v ddp , oe = v ih program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode ce = pgm program memory read mode v pp = v dd dc programming characteristics (t a = 25 5 c, v ss = 0 v) min. typ. max. unit 2.4 v ddp +0.3 v C0.3 0.8 v 10 m a 2.4 v 0.45 v 10 m a 10 m a 6.25 65 6.75 v 4.5 5.0 5.5 v 12.2 12.5 12.8 v v pp = v ddp v 30 ma 50 ma 50 ma 1 100 m a notes 1. refers to the symbol of the corresponding m pd27c1001a. 2. v ddp refers to the v dd pin in programming. symbol v ih v il i li v oh v ol i a9 i lo v ddp v pp i dd i pp
m pd78p324, 78p324(a) 63 ac programming characteristics (t a = 25 5 c, v ss = 0 v) in prom write mode parameter address setup time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time oe ? valid data delay time min. typ. max. unit 2 m s 2 m s 2 m s 2 m s 2 m s 0 130 ns 2 m s 2 m s 0.095 0.1 0.105 ms 2 m s 200 ns symbol note1 t as t ces t ds t ah t dh t df t vps t vds note 2 t pw t oes t oe condition notes 1. corresponds to the symbol of m pd27c1001a (t vds excluded). 2. the symbol of t vds on m pd27c1001a is t vcs . in prom read mode parameter address ? data output time ce ? data output time oe ? data output time data hold time (vs. oe - , ce - ) note 2 data hold time (vs. address) min. typ. max. unit 2 m s 1 m s 1 m s 0 130 ns 0ns symbol note1 t acc t ce t oe t df t oh condition ce = oe = v il oe = v il ce = v il ce = v il or oe = v il ce = oe = v il notes 1. corresponds to the symbol of m pd27c1001a. 2. t df refers to the time when either oe or ce became v ih first.
m pd78p324, 78p324(a) 64 prom write mode timing cautions 1. ensure to apply v ddp before v pp , and disconnect it after v pp . 2. ensure that v pp does not exceed +13.5 v even when the overshoot is included. 3. taking out or putting in while +12.5 v is applied to v pp may cause adverse effects on the reliability. prom read mode timing notes 1. to read within the range of t acc , please make sure that the delay time from ces falling edge of the oe input is up to t acc -t oe . 2. t df refers to the time when either oe or ce became v ih first. a0-a16 d0-d7 v pp v ddp v ddp + 1.5 v ddp v ih v il v ih v il v ih v il v pp v ddp ce pgm oe hi-z program program verify t ds t as t vps t vds t ces data output data input hi-z t ah hi-z t dh t df t pw t oes t oe note 1 t oe note 2 a0-a16 ce oe d0-d7 vailed address hi-z t acc data output hi-z t oh t df note 1
m pd78p324, 78p324(a) 65 8. package drawings 74-pin plastic qfp( n n 20) item millimeters inches f 1 f 2 i 2.0 1.0 0.20 q 0.079 0.039 0.008 s74gj-100-5bj-3 note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. c 20.0?.2 0.787 m 0.15 0.006 0.1?.1 0.004?.004 +0.004 ?.003 +0.009 ?.008 a 23.2?.4 0.913 h 0.40?.10 0.016 +0.004 ?.005 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 p 3.7 0.146 s 4.0 max. 0.158 max. +0.10 ?.05 b 20.0?.2 0.787 +0.009 ?.008 +0.017 ?.016 j 1.0 (t.p.) 0.039 (t.p.) r5 ? 5 ? d 23.2?.4 0.913 +0.017 ?.016 g 1 g 2 2.0 1.0 0.079 0.039 k 1.6?.2 0.063?.008 a b g 1 h ij c d p n k l m detail of lead end m 56 57 37 74 1 19 18 38 f 2 f 1 g 2 s q r remark the package and material of the es product are equivalent to those for mass production.
m pd78p324, 78p324(a) 66 p68l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 1.0 0.12 23.12 0.20 0.15 r 0.8 0.20 +0.10 ?.05 0.992 0.008 0.953 0.953 0.992 0.008 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.910 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005 +0.004 ?.002 +0.009 ?.008 n k m q a u 68 b d c 1 f e t p m g h ij 68 pin plastic qfj ( 950 mil) remark the package and material of the es product are equivalent to those for mass production.
m pd78p324, 78p324(a) 67 74 pin ceramic wqfn x74kw-100a-1 item millimeters inches note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. a b c d e f g h i j k q r s t u w y 20.0 0.4 18.0 18.0 20.0 0.4 1.94 2.14 4.0 max. 0.51 0.10 0.10 1.0 (t.p.) 1.0 0.2 c 0.3 2.0 2.0 r 2.0 10.0 0.7 0.2 c 1.5 0.787 0.709 0.709 0.787 0.076 0.084 0.158 max. 0.020 0.004 0.004 0.039 (t.p.) 0.039 c 0.012 0.079 0.079 r 0.079 0.394 0.028 c 0.059 +0.017 ?.016 +0.017 ?.016 +0.009 ?.008 +0.008 ?.009 a b d c t y u e f g i m k q s 74 h j 1 w r remark the package and material of the es product are equivalent to those for mass production.
m pd78p324, 78p324(a) 68 68 pin ceramic wqfn x68kw-50a-1 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. a b c d e f g h i j k l p q r s t u y 24.13 0.4 21.5 21.5 24.13 0.4 1.65 2.03 3.50 max. 0.64 0.10 0.12 1.27 (t.p.) 1.27 0.2 2.16 0.2 r 0.2 c 1.02 1.905 1.905 r 3.0 12.0 c 0.5 0.950 0.016 0.846 0.846 0.950 0.016 0.065 0.080 0.138 max. 0.025 0.005 0.05 (t.p.) 0.05 0.008 0.085 0.008 r 0.008 c 0.04 0.075 0.075 r 0.118 0.472 c 0.020 g a u f e y t b c d 68 j i m h r k l q p 1 s +0.005 ?.004 remark the package and material of the es product are equivalent to those for mass production.
m pd78p324, 78p324(a) 69 9. recommended soldering conditions please solder the package of this product under the conditions recommended as follows. for details of the recommended conditions for soldering, please refer to the information document semiconductor device mounting technology manual (iei-1207). for soldering methods and conditions other than those recommended below, please contact nec sales personnel. table 9-1. soldering conditions for surface-mount type (1) m pd78p324gj-5bj : 74-pin plastic qfp (20 x 20 mm) m pd78p324lp : 68-pin plastic qfj ( n n 950 mil) m pd78p324lp(a) : 68-pin plastic qfj ( n n 950 mil) m pd78p324lp(a1) : 68-pin plastic qfj ( n n 950 mil) m pd78p324lp(a2) : 68-pin plastic qfj ( n n 950 mil) soldering method soldering condition infrared reflow package peak temperature : 230 c; time : within 30 secs (210 c or more); count: once; day limit : 7 days note (hereafter, pre-baked for 36 hrs at 125 c) vps package peak temperature : 215 c; time : within 40 secs (200 c or more); count: once; day limit : 7 days note (hereafter, pre-baked for 36 hrs at 125 c) wave soldering solder bath temperature: no more than 260 c; time : within 10 secs; count: once; preheating temperature : 120 c max. (package surface temperature); day limit : 7 days note (hereafter, pre-baked for 36 hours at 125 c) pin part heating pin temperature : no more than 300 c; time : within 3 secs (per device side) recommended condition symbol ir30-367-1 vp15-367-1 ws60-367-1 note refers to the number of days for storage after the dry pack is opened. the storage conditions are 25 c and no more than 65 %rh. caution avoid using multiple soldering methods at the same time (except the pin part heating method).
m pd78p324, 78p324(a) 70 table 9-2. soldering conditions for surface-mount type (2) m pd78p324gj(a)-5bj : 74-pin plastic qfp (20 x 20 mm) m pd78p324gj(a1)-5bj : 74-pin plastic qfp (20 x 20 mm) m pd78p324gj(a2)-5bj : 74-pin plastic qfp (20 x 20 mm) soldering method soldering condition infrared reflow package peak temperature: 235 c; time: within 30 secs (210 c or more); count: twice; day limit: 7 days note (hereafter, pre-baked for 36 hrs at 125 c) (1) the second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) please avoid flux water washing after the first reflow. vps package peak temperature: 215 c; time: within 40 secs (200 c or more); count: within twice; day limit: 7 days note (hereafter, pre-baked for 36 hrs at 125 c) (1) the second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) please avoid flux water washing after the first reflow. wave soldering solder bath temperature: no more than 260 c; time: within 10 secs; count: once; preheating temperature: up to 120 c (package surface temperature); day limit: 7 days note (hereafter, pre-baked for 36 hours at 125 c) pin part heating pin temperature: no more than 300 c; time: within 3 secs (per device side) recommended condition symbol ir35-367-2 vp15-367-2 ws60-367-1 note refers to the number of days for storage after the dry pack is opened. the storage conditions are 25 c and no more than 65 %rh. caution avoid using two or more soldering methods at the same time (except the pin part heating method).
m pd78p324, 78p324(a) 71 appendix a. conversion socket package drawing and recommended substrate installation pattern figure a-1. conversion socket (ev-9200g-74) package drawing (reference) a f d 1 e b c c 1.5 m n l k r q p s t o i h ev-9200g-74 j g no.1 pin index ev-9200g-74-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s t 25.0 20.35 20.35 25.0 4-c 2.8 1.0 11.0 22.0 24.7 5.0 22.0 24.7 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.984 0.801 0.801 0.984 4-c 0.11 0.039 0.433 0.866 0.972 0.197 0.866 0.972 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 f f f f
m pd78p324, 78p324(a) 72 figure a-2. recommended pattern for conversion socket (ev-9200g-74) substrate installation (reference) f e g j k h i d a b c 0.039 0.709=0.709 0.039 0.709=0.709 ev-9200g-74-p0 item millimeters inches a b c d e f g h i j k 25.7 21.0 21.0 25.7 11.00 0.08 5.00 0.08 0.6 0.02 2.36 0.03 1.57 0.03 1.012 0.827 0.827 1.012 0.433 0.197 0.024 0.093 0.062 1.0 0.02 18=18.0 0.05 1.0 0.02 18=18.0 0.05 f f +0.002 ?.001 +0.002 ?.003 +0.002 ?.001 +0.002 ?.003 +0.004 ?.003 +0.003 ?.004 +0.001 ?.002 f f +0.001 ?.002 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (iei-1207). caution
m pd78p324, 78p324(a) 73 appendix b. tools b.1 development tools the following development tools have been made available for development of the system using the m pd78p324. language processors 78k/iii series relocatable assem- bler (ra78k/iii) 78k/iii series c compiler (cc78k/iii) refers to the relocatable assembler which can be used commonly for the 78k/iii series. equipped with the macro function, the relocatable assembler is aimed at improved development efficiency. the assembler is also accompanied by the structured assembler which can describe the program control structure explicitly, thus making it possible to improve the productivity and the maintainability of the program. host machine pc-9800 series ibm pc/at tm and its compatible machine hp9000 series 300 tm sparcstation tm supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc cartridge tape (qic-24) part number m s5a13ra78k3 m s5a10ra78k3 m s7b13ra78k3 m s7b10ra78k3 m s3h15ra78k3 m s3k15ra78k3 os ms-dos tm pc dos tm hp-ux tm sunos tm host machine pc-9800 series ibm pc/at and its compatible machine hp9000 series 300 sparcstation supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc cartridge tape (qic-24) part number m s5a13cc78k3 m s5a10cc78k3 m s7b13cc78k3 m s7b10cc78k3 m s3h15cc78k3 m s3k15cc78k3 os ms-dos pc dos hp-ux sunos refers to the c compiler which can be commonly used in the 78k/iii series. this compiler is a program converting the programs written in the c language to those object codes which are executable by microcomputers. when using this compiler, the 78k/iii series relocatable assembler (ra78k/iii) is required. remark relocatable assembler and c compiler operations are assured only on the host machine and the os above.
m pd78p324, 78p324(a) 74 pg-1500 unisite 2900 3900 note pa-78p324gj pa-78p324lp pa-78p324kc pa-78p324kd pg-1500 controller prom write tools this prom programmer is capable of programming by manipulating a prom- incorporated single-chip microcomputer from a stand-alone or host machine after connecting the accompanying board and the separately available programmer adapter. it can also program representative proms ranging from 256 kbits to 4 mbits. these are prom programmers made by data i/o japan. these are the prom programmer adapters for writing programs into the m pd78p324 on general-purpose prom programmer such as pg-1500. pa-78p324gj: for m pd78p324gj pa-78p324lp: for m pd78p324lp pa-78p324kc: for m pd78p324kc pa-78p324kd: for m pd78p324kd a pg-1500 and a host machine are connected with the serial interface or the parallel interface to control the pg-1500 on the host machine. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13pg1500 m s5a10pg1500 m s7b13pg1500 m s7b10pg1500 os ms-dos pc dos hardware software note being evaluated. remark the pg-1500 controller operation is assured only on the host machine and the os above.
m pd78p324, 78p324(a) 75 debugging tools ie-78327-r ie-78320-r note ep-78320gj-r ep-78320l-r ie-78327-r control program (ie controller) ie-78320-r control program note (ie controller) these are the in-circuit emulators which can be used for the development and debugging of application systems. debugging is performed by connecting them to a host machine. the ie-78327-r can be used commonly for both the m pd78322 subseries and the m pd78328 subseries. the ie-78320-r can be used for the m pd78322 subseries. these are the emulation probes for connecting the ie-78327-r or ie-78320-r to a target system. ep-78320gj-r: for 74-pin plastic qfp ep-78320l-r: for 68-pin plastic qfj this program is for controlling the ie-78327-r from a host machine. it can execute commands automatically, thus enabling more efficient debugging. hardware software host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13ie78327 m s5a10ie78327 m s7b13ie78327 m s7b10ie78327 os ms-dos pc dos this program is for controlling the ie-78320-r from a host machine. it can execute commands automatically, thus enabling more efficient debugging. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc part number m s5a13ie78320 m s5a10ie78320 m s7b10ie78320 os ms-dos pc dos remarks 1. the operation of each software is assured only on the host machine and the os above. 2. m pd78322 subseries: m pd78320, 78322, 78p322, 78323, 78324, 78p324, 78320(a), 78320(a1), 78320(a2), 78322(a), 78322(a1), 78322(a2), 78323(a), 78323(a1), 78323(a2), 78324(a), 78324(a1), 78324(a2), 78p324(a), 78p324(a1), 78p324(a2) m pd78328 subseries: m pd78327, 78328, 78p328, 78327(a), 78328(a) note the existing product ie-78320-r is a maintenance product. if you are going to newly purchase an in-circuit emulator, please use the alternative product ie-78327-r.
m pd78p324, 78p324(a) 76 development tool configurations note the socket is supplied with the emulation probe. remarks 1. it is also possible to use the host machine and the pg-1500 by connecting them directly by the rs- 232-c. 2. in the diagram above, representative software supply media and 3.5-inch fds. host machine pc-9800 series ibm pc/at or its compatible machine software relocatable assembler (with structured assembler) pg-1500 controller ie controller pd78p324gj pd78p324lp pd78p324kd pd78p324kc pa-78p324gj pa-78p324lp pa-78p324kc pa-78p324kd +++ programmer adapters prom-incorporated products rs-232-c ie-78327-r in-circuit emulator rs-232-c pg-1500 prom programmer emulation probes socket for connecting the emulation probe and the target system ep-78320gj-r ep-78320l-r ev-9200g-74 socket for plastic qfj target system m m m m note
m pd78p324, 78p324(a) 77 b.2 evaluation tools to evaluate the functions of the m pd78p324, the following tools are made available. part number eb-78320-98 eb-78320-pc function by connecting to a host machine, it is possible to evaluate the functions equipped by the m pd78p324 in a simple manner. the com- mand system of this product basically conforms to that of ie-78327-r and ie-78320- r. therefore, it is easy to move to the development work of application systems by ie-78327-r or ie-78320-r. in addition a turbo access manager ( m pd71p301) note can be mounted on the board. note the turbo access manager ( m pd71p301) is a maintenance product. cautions 1. this product is not a development tool of m pd78p324 application systems. 2. this product is not equipped with the emulation function for executing the prom incorporated in the m pd78p324. b.3 embedded software the following embedded software programs are available to perform program development and maintenance more efficiently. eeal-time os host machine pc-9800 series ibm pc/at or its compatible machine real-time os (rx78k/iii) the rx78k/iii is designed to provide a multi-task environment in the field of control application where real-time operation is required. by using this real-time os, the performance of the whole system can be improved by allocating cpus idle time to other processings. the rx78k/iii provides the system call based on the m itron specifications. the rx78k/iii package provides tools (configurators) for creating rx78k/iiis nucleus and multiple information table. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13rx78320 m s5a10rx78320 m s7b13rx78320 m s7b10rx78320 os ms-dos pc dos caution to purchase the operating system above, you need to fill in a purchase application form beforehand and sign a contract allowing you to use the software. remark when using the real-time os rx78k/iii, you need the assembler package ra78k/iii (optional) as well.
m pd78p324, 78p324(a) 78 fuzzy knowledge data creation tools (fe9000, fe9200) translator (ft78k3) note fuzzy inference module (fi78k/iii) note fuzzy inference debugger (fd78k/iii) this program supports inputting/editing/evaluating (through simulation) of the fuzzy knowledge data (fuzzy rules and membership functions). fuzzy inference development support system host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fe9000 m s5a10fe9000 m s7b13fe9000 m s7b10fe9000 os ms-dos pc dos winsows this program converts the fuzzy knowledge data obtained with fuzzy knowledge data creation tools to an assembler source program for ra78k/iii. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13ft78k3 m s5a10ft78k3 m s7b13ft78k3 m s7b10ft78k3 os ms-dos pc dos supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fi78k3 m s5a10fi78k3 m s7b13fi78k3 m s7b10fi78k3 os ms-dos pc dos supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fd78k3 m s5a10fd78k3 m s7b13fd78k3 m s7b10fd78k3 os ms-dos pc dos note under development host machine pc-9800 series ibm pc/at and its compatible machine this program executes fuzzy inference. fuzzy inference is executed by being linked to the fuzzy knowledge data converted by the translator. this is a support software program for evaluating and adjusting the fuzzy knowl- edge data at a hardware level by using the in-circuit emulator. host machine pc-9800 series ibm pc/at and its compatible machine
m pd78p324, 78p324(a) 79 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function. qtop is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corp. pc/at and pc dos are trademarks of ibm corp. hp9000 series 300 and hp-ux are trademarks of hewlett-packard. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron.
the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd78p324kc, 78p324kd the customer must judge the need for license: m pd78p324gj-5bj/(a)/(a1)/(a2)/, 78p324lp/(a)/(a1)/(a2) no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 m pd78p324, 78p324(a)

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